Scientific journal
European Journal of Natural History
ISSN 2073-4972

ACCURACY INCREASE AND SIMPLIFICATION OF PARALLEL ANALOG-TO-DIGITAL CODER MEANS

Bondar M.S., Mastepanenko M.A.
The known at present time methods of "voltage-code" converting significantly differ from each other with the converting rate, hardware implementation difficulty and potential accuracy. Undoubted leaders in the first two categories appear analog-to-digital coders (ADC). Thanks to the simultaneous work of  equalized comparator units paralleled to the source of home signal, the base voltage of which is formed by  resistors, the parallel ADC are the quickest. For example, one-of-eight decoder MAX 104 allows getting 1 billion indications per second.

But a disadvantage of a parallel ADC is a high complexity and, as the consequence of it, a high price (hundreds of US dollars) and a considerable power intake (about 4 W); the number of comparator units redoubling with the ADC code length (and it means its accuracy) increase. When the register length is more than 6-8 bits, the scheme becomes extremely bulky. This is what limits the use of parallel ADC in practice.

The research carried out by the authors showed that one of the most optimal ways of accuracy increase and simplification of parallel ADC means, which are used for bipolar signals conversion, can serve introducing a sense and negative voltage inversion unit, completing activity of sensing (the polarity) of home signal voltage, creation of voltage module of home signal and its following relaying with a unitary ratio of transmission, into the ADC composition scheme

Introducing the offered unit into the composition of one-of- n ADC means for analog-to-digital processing of bipolar signals and negative polarity signals is equal to:

  1. output pattern increase by one digit on account of introducing an additional bit (the polarity sign code), and the ADC accuracy increase being meant by it without saying;
  2. simplification of ADC means on account of negative voltage inversion, that will allow reducing ADC code length from n to (n-1), and it means - reducing the number of comparators twice as much;
  3. reducing power consumption (in terms of one digit of a parallel ADC) practically twice as much on account of the means´ simplification.

The article is admitted to the International Scientific Conference " Information delivery and processing problems "; 2007, India, Goa, 2007, March 1-11; came to the editorial office on 11.01.07